Priority is claimed to Japanese Patent Application Number JP2005-280520 filed on Sep. 27, 2005, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device which achieves reduction in device size by suppressing extension of diffusion of its isolation region, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In a conventional semiconductor device, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of island regions by a P type isolation region. Formed in each of the island regions is, for example, an N channel type MOS transistor, a P channel type MOS transistor, an NPN bipolar transistor, or the like. The P type isolation region is diffused by a thermal diffusion method in a direction of the depth and in a direction of the width of the substrate and the epitaxial layer, to form PN junction regions with the N type epitaxial layer. This technology is described for instance in Japanese Patent Application Publication No. 2003-197793, pp. 5 and 6, and FIG. 1.
In the conventional semiconductor device, each of diffusion layers which constitute the isolation region is diffused in a direction of the depth and in a direction of the width as mentioned above. Various elements such as the N channel type MOS transistor are formed in the regions which are partitioned by the isolation region. Here a P type diffusion layer which constitutes the isolation region forms the PN junction regions with a lowest-concentration N type region such as the epitaxial layer which constitutes the element. However, the conventional semiconductor device has the problem that it is difficult to achieve reduction in device size, since the P type diffusion layer which constitutes the isolation region diffuses widely in a direction of the width, where its extension of diffusion is not suppressed, because of a structure in which the P type diffusion layer is in contact with the lowest-concentration N type region.
Moreover, in a conventional method of manufacturing a semiconductor device, a P type buried diffusion layer is formed from a boundary between a substrate and an epitaxial layer, a P type diffusion layer is formed from the surface of the epitaxial layer, and isolation region is formed by coupling the both diffusion layers. The P type buried diffusion layer diffuses widely in a direction of the width because of containing a high concentration of impurities and hence requiring a long time for heat treatment. Accordingly, there is a problem that it is difficult to achieve reduction in device size.